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EM78P860 8 -BIT MICRO-CONTROLLER
I.
GENERAL DESCRIPTION
The EM78P860 is an 8-bit RISC type microprocessor with low power , high speed CMOS technology . Integrated onto a single chip are on_chip watchdog (WDT) , RAM , ROM , programmable real time clock /counter , internal interrupt , power down mode , LCD driver and tri-state I/O . The EM78P860 provides a single chip solution to design a message display .
II.
FEATURES
CPU * Operating voltage range : 2.5V~5.5V * 16Kx13 on chip ROM * 2.8Kx8 on chip RAM * Up to 32 bi-directional tri-state I/O ports * 8 Level stack for subroutine nesting * 8-bit real time clock/counter (TCC) * Two sets of 8 bit counters can be interrupt sources * Selective signal sources and with overflow interrupt * Programmable free running on chip watchdog timer * 99.9% single instruction cycle commands * Four modes (internal clock 3.679MHz, external 32.768KHz) 1. Sleep mode : CPU and 3.679MHz clock turn off, 32.768KHz clock turn off 2. Idle mode : CPU and 3.679MHz clock turn off, 32.768KHz clock turn on 3. Green mode : 3.679MHz clock turn off, CPU and 32.768KHz clock turn on 4. Normal mode : 3.679MHz clock turn on , CPU and 32.768KHz clock turn on * Low battery detector * Input port wake up function * 8 interrupt source , 4 external , 3 internal * 100 pin QFP (EM78860AQ, POVD disable) (EM78860BQ, POVD enable) or chip (EM78860H) * Port key scan function * Port interrupt , pull high and open drain functions * Clock frequency 32.768KHz externally LCD * LCD operation voltage chosen by software * Common driver pins : 16 * Segment driver pins : 60 * 1/4 bias * 1/8,1/16 duty
III. APPLICATION
1. adjunct units
* This specification is subject to be changed without notice.
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IV. PIN ASSIGNMENTS
SEG41 SEG40 SEG39 SEG38 SEG37 SEG36 RESET P7.7 P7.6 P7.5 P7.4 P7.3/INT3 P7.2/INT2 P7.1/INT1 P7.0/INT0 COM15/P6.7 COM14/P6.6 COM13/P6.5 COM12/P6.4 COM11/P6.3 COM10/P6.2 COM9/P6.1 COM8/P6.0 COM7 COM6 COM5 COM4 COM3 GND COM2
SEG42 SEF43 TEST SEG44/P8.0 SEG45/P8.1 SEG46/P8.2 SEG47/P8.3 SEG48/P8.4 SEG49/P8.5 SEG50/P8.6 SEG51/P8.7 SEG52/P9.0 SEG53/P9.1 SEG54/P9.2 SEG55/P9.3 SEG56/P9.4 SEG57/P9.5 SEG58/P9.6 SEG59/P9.7 VDD1
81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100
80 79 78 77 76 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51
EM78P860
50 49 48 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31
COM1 COM0 SEG35 SEG34 SEG33 SEG32 SEG31 SEG30 SEG29 SEG28 SEG27 SEG26 SEG25 SEG24 SEG23 SEG22 SEG21 SEG20 SEG19 SEG18
V.
FUNCTIONAL BLOCK DIAGRAM
CPU
GND NC PLLC NC NC NC NC NC XIN XOUT VDD SEG0 SEG1 SEG2 SEG3 SEG4 SEG5 SEG6 SEG7 SEG8 SEG9 SEG10 SEG11 SEG12 SEG13 SEG14 SEG15 SEG16 VDD2 SEG17
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
Fig. 1 Pin assignments
ROM
RAM
CLK
TIMING CONTROL
I/O PORT
I/O PORT
INPUT PORT TIMER LCD LATCH & DRIVER
INPUT PORT
LCD OUTPUT
Fig. 2 Functional block diagram1
* This specification is subject to be changed without notice.
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EM78P860 8 -BIT MICRO-CONTROLLER
XIN
XOUT
WDT Timer
Oscillator/Timing Control
Prescaler
ROM
R2
Stack
R1(TCC)
GENERAL RAM
Interrupt Controller
Instruction register
ALU
Control of sleep and wake-up on I/O ports
RAM
Instruction Decoder R4
R3 R5
ACC
DATA & CONTROL BUS
2.5K RAM
PORT6 IOC6 R6
PORT7 IOC7 R7
PORT8 IOC8 R8
PORT9 IOC9 R9
P60~P67
P70~P77
P80~P87
P90~P97
Fig. 2 Functional block diagram2
VI.
PIN DESCRIPTIONS
Type POWER POWER I O I O O (PORT6) O (PORT8) O (PORT9) PORT7(0) PORT7(1) PORT7(2) PORT7(3) PORT7 Function Power Gound Input pin for 32.768 kHz oscillator Output pin for 32.768 kHz oscillator Phase loop lock capacitor, connect a capacitor 0.01 to 0.047 with GND Common driver pins of LCD drivers Segment driver pins of LCD drivers PORT9 AS FUNCTION KEY CAN WAKE UP WATCHDOG. PORT7(0)~PORT7(3) signal can be interrupt signals.
Symbol VDD GND XTin XTout PLLC COM0..COM7 COM8..COM15 SEG0..SEG43 SEG44..SEG51 SEG52..SEG59 INT0 INT1 INT2 INT3 P7.0~P7.7
P6.0~P6.7 P8.0~P8.7 P9.0~P9.7 TEST RESET
PORT6 PORT8 PORT9 I I
PORT 7 can be INPUT or OUTPUT port each bit. Internal Pull high function. Key scan function. Bit6,7 open drain function. PORT 6 can be INPUT or OUTPUT port each bit. And shared with Common signal. PORT 8 can be INPUT or OUTPUT port each bit. And shared with Common signal. PORT 9 can be INPUT or OUTPUT port each bit. And shared with Common signal. Test pin into test mode , normal low
* This specification is subject to be changed without notice.
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VII. FUNCTION DESCRIPTION
VII.1 Operational Registers 1. R0 (Indirect Addressing Register) R0 is not a physically implemented register. It is useful as indirect addressing pointer. Any instruction using R0 as register actually accesses data pointed by the RAM Select Register (R4). 2. R1 (TCC) * Increased by an internal signal edge applied to TCC , or by the instruction cycle clock. * Written and read by the program as any other register. R2 (Program Counter) * The structure is depicted in Fig. 4. * Generates 16Kx13 on-chip ROM addresses to the relative programming instruction codes. * "JMP" instruction allows the direct loading of the low 10 program counter bits. * "CALL" instruction loads the low 10 bits of the PC, PC+1, and then push into the stack.. * "RET'' ("RETL k", "RETI") instruction loads the program counter with the contents at the top of stack. * "MOV R2,A" allows the loading of an address from the A register to the PC, and the ninth and tenth bits are cleared to "0''. * "ADD R2,A" allows a relative address be added to the current PC, and contents of the ninth and tenth bits are cleared to "0''. * "TBL" allows a relative address be added to the current PC, and contents of the ninth and tenth bits don't change. * The most significant bit (A10~A13) will be loaded with the content ofbit PS0~PS3 in the status register (R5) upon the execution of a "JMP'', "CALL'', "ADD R2,A'', or "MOV R2,A'' instruction.
3.
CALL PC A13 A12 A11 A10 A9 A8 A7~A0 RET RETTL RETI Stack 1 Stack 2 Stack 3 Stack 4 Stack 5 Stack 6 Stack 7 Stack 8
0000 PAGE0 0000~03FF
0000 PAGE1 0400~07FF
0000 PAGE2 0800~0BFF
1110 PAGE14 3800~3BFF
1111 PAGE15 3C00~3FFF
Fig. 4 Program counter organization
* This specification is subject to be changed without notice.
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ADDRESS 00 01 02 03 04 05 06 07 08 09 0A 0B 0C 0D 0E 0F 10 : 1F 20 : 3F
REGISTER CONTROL REGISTER (PAGE0) CONTROL REGISTER (PAGE1)
R0 R1(TCC) R2(PC) R3(STATUS) R4(RSR) R5(ROM PAGE) R6(PORT6) R7(PORT7) R8(PORT8) R9(PORT9) RA(CLK) RB() RC(2.5K RAM ADRESS) RD(2.5K RAM DATA) RE RF(INT FLAG)
page0 IOC6 IOC7 IOC8 IOC9 IOCA IOCB(LCD ADDRESS) IOCC(LCD DATA) IOCD(PULL HIGH) IOCE(IO, LCD) IOCF(INT CONTROL)
page1
IOCB(COUNTER1) IOCC(COUNTER2)
16x8 Common Register
BANK0~BANK3 32X8 ~ 32X8 REGISTER
RC(ADDRESS) RD(DATA)
0 : 255
BAND1 256X8
BAND1 256X8
............ ............
BAND10 256X8
Fig. 5 Data memory configuration 4. R3 ( Status Register ) 7 * Bit 0 (C) : * Bit 1 (DC) : * Bit 2 (Z) : * Bit 3 (P) : * Bit 4 (T) : 6 PAGE 5 4 T 3 P 2 Z 1 DC 0 C
Carry flag Auxiliary carry flag Zero flag Power down bit. Set to 1 during power on or by a "WDTC" command and reset to 0 by a "SLEP" command. Time-out bit. Set to 1 by the "SLEP" and "WDTC" command, or during power up and reset to 0 by WDT time out. T 0 0 1 1 x P 0 1 0 1 x REMARK
EVENT WDT TIME OUT sleep mode WDT time out (not sleep mode /RESET wake up from sleep power up Low pulse on /RESET
x . . don't care
* Bit 5 : unused * Bit 6 PAGE : changed IOCB~IOCE to another page, 0/1page0/page1 * Bit 7 unused
* This specification is subject to be changed without notice.
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EM78P860 8 -BIT MICRO-CONTROLLER
5.
R4 ( RAM Select Register ) * Bit 0 ~ 5 are used to select up to 64 register in the indirect addressing mode. * Bit 6 ~ 7 determine which bank is actived among the 4 banks. * See the configuration of the data memory in Fig. 4.
6.
R5 ( Program Page Select Register) 7 6 5 4 3 PS3 2 PS2 1 PS1 0 PS0
* Bit 0 (pS0) ~ 3 (PS3) Page selec bits. Page select bits PS3 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 PS2 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 program memory page (Address) Page 0 Page 1 Page 2 Page 3 Page 4 page 5 Page 6 Page 7 Page 8 Page 9 Page 10 Page 11 Page 12 Page 13 Page 14 Page 15
* User can use PAGE instruction to change page. To maintain program page by user. Otherwise, user can use far jump (FJMP) or far call (FCALL) instructions to program user's code. And the program page is maintained by EMC's complier. It will change user's program by inserting instruction within program. * Bit4~7 : unused 7. R6 ~R9 ( Port 6 ~ Port 9) * Five 8-bit I/O registers. 8. RA 7 IDLE 6 /358E 5 /LPD 4 /LOW-BAT 3 0 2 0 1 0 0 0
* Bit0 ~ Bit3 unused, please set to "0"
* This specification is subject to be changed without notice.
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EM78P860 8 -BIT MICRO-CONTROLLER
* Bit4(Read Only)(Low battery signal) 0/1 = Battery voltage is low/Normal . If the battery voltage is under 3.6V then sends a `0' signal to RA register bit4 or a `1' signal to this Bit if VDD is over 3.8V. * Bit5(read/Write)(Low battery detect enable) 0/1 = low battery detect DISABLE/ENABLE. The relation between /LPD,/POVD and /LOW_BAT can see Fig 6.
Vdd /POVD /LPD
s2 1 on 0 off
to Low bat + 1 on Vref
s2 1 on 0 off
1 on To rese t
/LPD
Fig. 6 The relation between /LPD,/POVD * Bit6(read/write)(PLL enable signal) 0/1=DISABLE/ENABLE The relation between 32.768K and 3.679M can see Fig. 7.
32.768K
PLL 3.679M 1 switch /358E 0 To system clock
Fig. 7 The relation between 32.768K and 3.679K . * Bit7 IDLE: sleep mode selection bit 0/1=sleep mode/IDLE mode. This bit will decide SLEP instruction which mode to go. These IDLE mode can be waken up by TCC clock or Watch Dog or PORT9 and run from "SLEP" next instruction. These SLEEP mode can be waken up by Watch Dog or PORT9 and run from address "00". SLEEP mode RA(7,6)=(0,0) + SLEP X IDLE mode RA(7,6)=(1,0) + SLEP Wake-up + Interrupt + Next instruction Wake-up + Next instruction Wake-up + Next instruction GREEN mode RA(7,6)=(x,0) no SLEP Interrupt NORMAL mode RA(7,6)=(x,1) no SLEP Interrupt
TCC time out
WDT time out Port9 wake-up
RESET RESET
RESET RESET
RESET RESET
* This specification is subject to be changed without notice.
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EM78P860 8 -BIT MICRO-CONTROLLER
9. RB Empty register, please don't use. 10. RC(2.5k RAM address)(read/write) 7 CIDA7 6 CIDA6 5 CIDA5 4 CIDA4 3 CIDA3 2 CIDA2 1 CIDA1 0 CIDA0
* Bit 0 ~ Bit 7 select CALLER ID RAM address up to 256. 11. RD(2.5k RAM address)(read/write) * Bit 0 ~ Bit 8 are CALLER ID RAM data transfer register. User can see IOCA register how to select CID RAM banks. 12.RE(LCD Driver,WDT Control)(read/write) 7 6 /WDTE 5 /WUP9H 4 /WUP9L 3 /WURING 2 LCD_C2 1 LCD_1 0 LCD_M
* Bit0 (LCD_M):LCD_M decides the methods, including duty, bias, and frame frequency. * Bit1~Bit2 (LCD_C#):LCD_C# decides the LCD display enable or blanking. change the display duty must set the "LCD_C2,LCD_C1" to "00". LCD_C2,LCD_C1 0 0 0 1 1 1 LCD Display Control Change duty Disable(turn off LCD) Blanking LCD display enable LCD_M 0 1 : : duty 1/16 1/8 : : bias 1/4 1/4
* Bit3 unused. Please set to "0" * Bit4(/WUP9L, PORT9 low nibble Wake Up Enable) : used to enable the wake-up function of low nibble in PORT9, (1/0=enable/disable) * Bit5 (/WUP9H, PORT9 high nibble WAKE Up Enable) : used to enable the wake-up function of high nibble in PORT9, (1/0=enable/disable) * Bit6 (/WDTE, Watch Dog Timer Enable) Control bit used to enable Watchdog timer. (1/0=enable/disable) * Bit7 unused 13. RF (Interrupt Status Register) 7 INT3 * * * * * * * 6 5 C8_2 4 C8_1 3 INT2 2 INT1 1 INT0 0 TCIF
"1" means interrupt request, "0" means non-interrupt Bit 0 (TCIF) TCC timer overflow interrupt flag. Set when TCC timer overflows . Bit 1 (INT0) external INT0 pin interrupt flag . Bit 2 (INT1) external INT1 pin interrupt flag . Bit 3 (INT2) external INT2 pin interrupt flag . Bit 4 (C8_1) internal 8 bit counter interrupt flag . Bit 5 (C8_2) internal 8 bit counter interrupt flag .
* This specification is subject to be changed without notice.
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EM78P860 8 -BIT MICRO-CONTROLLER
* * * *
Bit 6 :unused. Please set to `0'. Bit 7 (INT3) external INT3 pin interrupt flag. High to low edge trigger , Refer to the Interrupt subsection. IOCF is the interrupt mask register. User can read and clear.
14.R10~R3F (General Purpose Register) * R10~R3F (Banks 0~3) all are general purpose registers. VII.2 Special Purpose Registers 1. A (Accumulator) * Internal data transfer, or instruction operand holding * It's not an addressable register. 2. CONT (Control Register) 7 6 INT 5 TS 4 3 PAB 2 PSR2 1 PSR1 0 PSR0
* Bit 0 (PSR0) ~ Bit 2 (PSR2) TCC/WDT prescaler bits. PSR2 0 0 0 0 1 1 1 1 PSR1 0 0 1 1 0 0 1 1 PSR0 0 1 0 1 0 1 0 1 TCC Rate 1:2 1:4 1:8 1:16 1:32 1:64 1:128 1:256 WDT Rate 1:1 1:2 1:4 1:8 1:16 1:32 1:64 1:128
* Bit 3 ( PAB ) : Prescaler assignment bit 0/1: TCC/WDT * Bit 4 : unused * Bit 5 ( TS ) : TCC signal source 0 : internal instruction cycle clock 1 : 16.38KHz * Bit 6 (INT) : INT enable flag 0 : interrupt masked by DISI or hardware interrupt 1 : interrupt enabled by ENI/RETI instructions * Bit 7 : unused * CONT register is readable and writable.
* This specification is subject to be changed without notice.
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EM78P860 8 -BIT MICRO-CONTROLLER
3.
IOC6 ~ IOC9 ( I/O Port Control Register ) * Five I/O direction control registers. * "1" put the relative I/O pin into high impedance, while "0" put the relative I/O pin as output. * User can see IOCB register how to switch to normal I/O port. IOCA (RAM,IO ,PAGE Control Register)(read/write,initial "00000000") 7 P8SH * Bit0 unused * Bit4~Bit1: "000" to "1001" are ten blocks of RAM area. User can use 2.5K RAM with RC ram address. * Bit 5 unused * Bit6: port8 low nibble switch, 0/1= normal I/O port/SEGMENT output . * Bit7: port8 high nibble switch , 0/1= normal I/O port/SEGMENT output 6 P8SL 5 0 4 CALL_4 3 CALL_3 2 CALL_2 1 CALL_1 0 0
4.
5.
IOCB (LCD ADDRESS) PAGE0 : Bit6 ~ Bit0 = LCDA6 ~ LCDA0 The LCD display data is stored in the data RAM . The relation of data area and COM/SEG pin is as below: COM15 ~ COM8 40H (Bit15 ~ Bit8) 41H : : 7BH 7CH 7DH 7EH 7FH COM7 ~ COM0 00H (Bit7 ~ Bit0) 01H : : 3BH 3CH 3DH 3EH 3FH
SEG0 SEG1 : : SEG59 Empty Empty Empty Empty
PAGE1 : 8 bit up-counter (COUNTER1) preset and read out register . ( write = preset ) . After an interruption, it will count from "00". 6. IOCC (LCD DATA) PAGE0 : Bit7 ~ Bit0 = LCD RAM data register PAGE1 : 8 bit up-counter (COUNTER2) preset and read out register. (write=preset) After a interruption, it will count from "00". 7. IOCD (Pull-high Control Register) 7 PH7 6 PH6 5 PH5 4 PH4 3 PH3 2 PH2 1 PH1 0 PH0
* Bit 0 ~ 7 (/PH#) Control bit used to enable the pull-high of PORT7(#) pin. 1: Enable internal pull-high 0: Disable internal pull-high
* This specification is subject to be changed without notice.
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EM78P860 8 -BIT MICRO-CONTROLLER
8. IOCE (Bais, PLL Control Register) PAGE0: 7 P9SH 6 P9SL 5 P6S 4 Bias3 3 Bias2 2 Bias1 1 0 0 SC
* Bit 0 :SC (SCAN KEY signal ) 0/1 = disable/enable. Once you enable this bit , all of the LCD signal will have a low pulse during a common period. This pulse has 30us width. Please use the procedure to implement the key scan function. a. set port7 as input port b. set IOCD page0 port7 pull high c. enable scan key signal d. Once push a key . Set RA(6)=1 and switch to normal mode. e. Blank LCD. Disable scan key signal. f. Set P6S =0. Port6 sent probe signal to port7 and read port7. Get the key. g. Note!! A probe signal should be delay a instruction at least to another probe signal. h. Set P6S =1. Port6 as LCD signal. Enable LCD.
KEY5 P63 KEY2 P62 KEY3 P61 KEY4 P60 KEY1
P73
P72
P71
P70
Fig. 8 Key scan circuit
VDD V1 V2 V3 V4 VLCD GND
com2
seg
VDD V1 V2 V3 V4 VLCD GND
30s
Fig. 9 Key scan signal
* This specification is subject to be changed without notice.
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EM78P860 8 -BIT MICRO-CONTROLLER
* Bit 1 : zero * Bit 2~4 (Bias1~Bias3) Control bits used to choose LCD operation voltage . LCD operate voltage Vop (VDD 5V) VDD=5V 000 0.60VDD 3.0V 001 0.66VDD 3.3V 010 0.74VDD 3.7V 011 0.82VDD 4.0V 100 0.87VDD 4.4V 101 0.93VDD 4.7V 110 0.96VDD 4.8V 111 1.00VDD 5.0V * Bit5:port6 switch , 0/1= normal I/O port/COMMON output * Bit6:port9 low nibble switch , 0/1= normal I/O port/SEGMENT output . Bit7:port9 high nibble switch PAGE1 : 7 OP77 6 OP76 5 C2S 4 C1S 3 PSC1 2 PSC0 1 0 -
* Bit0: unused, please set to `0' * Bit1: unused, please set to `0` * Bit3~Bit2: counter1 prescaler , reset=(0,0) (PSC1,PSC0) = (0,0)=>1:1 , (0,1)=>1:2 , (1,0)=>1:4 , (1,1)=>1:8 * Bit4:counter1 source , (0/1)=(32768Hz/3.679MHz if enable) * Bit5:counter2 source , (0/1)=(32768Hz/3.679MHz if enable) scale=1:1 * Bit6:P76 opendrain control (0/1)=(disable/enable) * Bit7:P77 opendrain control (0/1)=(disable/enable) 9. IOCF (Interrupt Mask Register) 7 INT3 6 5 C8_2 4 C8_1 3 INT2 2 INT1 1 INT0 0 TCIF
* Bit 0 ~ 7 interrupt enable bit. 0: disable interrupt 1: enable interrupt * IOCF Register is readable and writable. It is very important to save ACC,R3 and R5 when processing a interruption. Address Instruction Note 0x08 DISI ;Disable interrupt 0x09 MOV A_BUFFER,A ;Save ACC 0x0A SWAP A_BUFFER 0x0B SWAPA 0x03 ;Save R3 status 0x0C MOV R3_BUFFER,A 0x0D MOV A,0x05 ;Save ROM page register 0x0E MOV R5_BUFFER,A : : : : : MOV A,R5_BUFFER ;Return R5 : MOV 0X05,A : SWAPA R3_BUFFER ;Return R3 : MOV 0X03,A : SWAPA A_BUFFER ;Return ACC : RETI
* This specification is subject to be changed without notice.
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EM78P860 8 -BIT MICRO-CONTROLLER
VII.3 TCC/WDT Prescaler There is an 8-bit counter available as prescaler for the TCC or WDT. The prescaler is available for the TCC only or WDT only at the same time. * An 8 bit counter is available for TCC or WDT determined by the status of the bit 3 (PAB) of the CONT register. * See the prescaler ratio in CONT register. * Fig. 10 depicts the circuit diagram of TCC/WDT. * Both TCC and prescaler will be cleared by instructions which write to TCC each time. * The prescaler will be cleared by the WDTC and SLEP instructions, when assigned to WDT mode. * The prescaler will not be cleared by SLEP instructions, when assigned to TCC mode.
CLK(=Fosc/2) Data Bus
0 TCC (32K CLK) 1 M U X
1 0 M U X SYNC 2 cycle TCC(R1)
TE
TS
PAB
TCC overflow interrupt
0 WDT 1
M U X
8-bit Counter
8-to-1 MUX PAB WDTE MUX PAB
PSR0~PSR2
WDT timeout
Fig. 10 Block diagram of TCC WDT VII.4 Ports I/O The I/O registers, Port 6 ~ Port 9, are bi-directional tri-state I/O ports. Port 7 can be pulled-high internally by software control. The I/O ports can be defined as "input" or "output" pins by the I/O control registers (IOC6 ~ IOC9 ) under program control. The I/O registers and I/O control registers are both readable and writable. The I/O interface circuit is shown in Fig. 11.
* This specification is subject to be changed without notice.
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EM78P860 8 -BIT MICRO-CONTROLLER
PCRD
Q PR D CLK Q CL PCWR
PORT
Q PR D CLK Q CL PDWR PDRD 0 1 M U X
IOD
Fig. 11 The circuit of I/O port and I/O control register VII.5RESET and Wake-up The RESET can be caused by (1) Power on reset, or Voltage detector (2) WDT timeout. (if enabled and in GREEN or NORMAL mode) Note that only Power on reset, or only Voltage detector in Case(1) is enabled in the system by CODE Option bit. If Voltage detector is disabled, Power on reset is selected in Case (1). Refer to Fig. 12.
VDD Oscillator DQ CLK CLR
CLK
Power-on Reset
1 0
M U X
Voltage Detector /Enable Code Option
WDTE WDT timeout WDT 18 ms
RESET
Fig. 12 Block diagram of Reset of controller
* This specification is subject to be changed without notice.
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EM78P860 8 -BIT MICRO-CONTROLLER
Once the RESET occurs, the following functions are performed. * * * * * * * The oscillator is running, or will be started. The Program Counter (R2) is set to all "0". When power on, the upper 3 bits of R3 and the upper 2 bits of R4 are cleared. The Watchdog timer and prescaler are cleared. The Watchdog timer is disabled. The CONT register is set to all "1" The other register (bit7..bit0) R5 = "00000000" R6 = PORT R7 = PORT R8 = PORT R9 = PORT RA = "010x0xxx RB = "11111111" RC = "00000000" RD = "xxxxxxxx" RE = "00000000" RF = "00000000"
IOC6 = "11111111" IOC7 = "11111111" IOC8 = "11111111" IOC9 = "11111111" IOCA = "00000000" Page0 IOCB = "00000000" Page0 IOCC = "0xxxxxxx" Page0 IOCD = "00000000" Page0 IOCE = "00000000" IOCF = "00000000"
Page1 IOCB = "00000000" Page1 IOCC = "00000000" Page1 IOCE = "00000000"
The controller can be awakened from SLEEP mode or IDLE mode (execution of "SLEP" instruction, named as SLEEP MODE or IDLE mode) by (1)TCC time out (IDLE mode only) (2) WDT time-out (if enabled) or, (3) external input at PORT9 . The three cases will cause the controller wake up and run from next instruction in IDLE mode , reset in SLEEP mode . After wake-up , user should control WATCH DOG in case of reset in GREEN mode or NORMAL mode. The last two should be open RE register before into SLEEP mode or IDLE mode. The first one case will set a flag in RF bit0 . And it will go to address 0x08 when TCC generate a interrupt . VII.6Interrupt The chip has internal interrupts which are falling edge triggered, as followed : TCC timer overflow interrupt (internal) , two 8-bit counters overflow interrupt . If these interrupt sources change signal from high to low , then RF register will generate `1' flag to corresponding register if you enable IOCF register. RF is the interrupt status register which records the interrupt request in flag bit. IOCF is the interrupt mask register. Global interrupt is enabled by ENI instruction and is disabled by DISI instruction. When one of the interrupts (when enabled) generated, will cause the next instruction to be fetched from address 008H. Once in the interrupt service routine the source of the interrupt can be determined by polling the flag bits in the RF register. The interrupt flag bit must be cleared in software before leaving the interrupt service routine and enabling interrupts to avoid recursive interrupts. There are four external interrupt pins including INT0 , INT1 , INT2 , INT3 . And four internal counter interrupt available. External interrupt INT0 , INT1 , INT2 , INT3 signals are from PORT7 bit0 to bit3 . If IOCF is enable then these signal will cause interrupt , or these signals will be treated as general input data . After reset, the next instruction will be fetched from address 000H and the instruction inturrept is 001H and the hardware inturrept is 008H. TCC will go to address 0x08 in GREEN mode or NORMAL mode after time out. And it will run next instruction from "SLEP" instruction and then go to address 0x08 in IDLE mode . These three cases will set a RF flag.
* This specification is subject to be changed without notice.
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EM78P860 8 -BIT MICRO-CONTROLLER
It is very important to save ACC,R3 and R5 when processing a interruption. Address 0x08 0x09 0x0A 0x0B 0x0C 0x0D 0x0E : : : : : : : : VII.7 Instruction Set Instruction set has the following features: (1) Every bit of any register can be set, cleared, or tested directly. (2) The I/O register can be regarded as general register. That is, the same instruction can operates on I/O register. The symbol "R" represents a register designator which specifies which one of the 64 registers (including operational registers and general purpose registers) is to be utilized by the instruction. Bits 6 and 7 in R4 determine the selected register bank. "b'' represents a bit field designator which selects the number of the bit, located in the register "R'', affected by the operation. "k'' represents an 8 or 10-bit constant or literal value. INSTRUCTION BINARY 0000 0000 0000 0000 0000 0001 0000 0000 0010 0000 0000 0011 0000 0000 0100 0000 0000 rrrr 0000 0000 0000 0000 0001 0001 0001 0001 0000 0001 0010 0011 STATUS AFFECTED None C None T,P T,P None None None None None None None Z,C,DC None Z Z Instruction DISI MOV A_BUFFER,A SWAP A_BUFFER SWAPA 0x03 MOV R3_BUFFER,A MOV A,0x05 MOV R5_BUFFER,A : : MOV A,R5_BUFFER MOV 0X05,A SWAPA R3_BUFFER MOV 0X03,A SWAPA A_BUFFER RETI Note ;Disable interrupt ;Save ACC ;Save R3 status ;Save ROM page register
;Return R5 ;Return R3 ;Return ACC
0 0 0 0 0 0 0 0 0 0
HEX 0000 0001 0002 0003 0004 000r 0010 0011 0012 0013 0014 001r 0020 00rr 0080 00rr
MNEMONIC NOP DAA CONTW SLEP WDTC IOW R ENI DISI RET RETI CONTR IOR R TBL MOV R,A CLRA CLR R
OPERATION No Operation Decimal Adjust A ACONT 0WDT, Stop oscillator 0WDT AIOCR Enable Interrupt Disable Interrupt [Top of Stack] PC [Top of Stack] PC Enable Interrupt CONTA IOCRA R2+A Bits 8~9 of R2 unchange AR 0A 0R
0 0000 0001 0100 0 0000 0001 rrrr 0 0 0 0 0000 0000 0000 0000 0010 01rr 1000 11rr 0000 rrrr 0000 rrrr
* This specification is subject to be changed without notice.
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EM78P860 8 -BIT MICRO-CONTROLLER
INSTRUCTION BINARY 0001 00rr rrrr 0001 01rr rrrr 0001 10rr rrrr 0001 11rr rrrr 0010 00rr rrrr 0010 01rr rrrr 0010 10rr rrrr 0010 11rr rrrr 0011 00rr rrrr 0011 01rr rrrr 0011 10rr rrrr 0011 11rr rrrr 0100 00rr rrrr 0100 01rr rrrr 0100 10rr rrrr 0100 11rr rrrr 0101 00rr rrrr 0101 01rr rrrr 0101 10rr rrrr 0101 11rr rrrr 0110 00rr rrrr STATUS AFFECTED Z,C,DC Z,C,DC Z Z Z Z Z Z Z Z Z,C,DC Z,C,DC Z Z Z Z Z Z None None C C C C None None None None None None None None None None None Z Z Z None None None Z,C,DC
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
HEX 01rr 01rr 01rr 01rr 02rr 02rr 02rr 02rr 03rr 03rr 03rr 03rr 04rr 04rr 04rr 04rr 05rr 05rr 05rr 05rr 06rr 06rr 06rr 06rr 07rr 07rr 07rr 07rr 0xxx 0xxx 0xxx 0xxx 1kkk 1kkk 18kk 19kk 1Akk 1Bkk 1Ckk 1Dkk 1E01 1E8k 1Fkk
MNEMONIC SUB A,R SUB R,A DECA R DEC R OR A,R OR R,A AND A,R AND R,A XOR A,R XOR R,A ADD A,R ADD R,A MOV A,R MOV R,R COMA R COM R INCA R INC R DJZA R DJZ R RRCA R RRC R RLCA R RLC R SWAPA R SWAP R JZA R JZ R BC R,b BS R,b JBC R,b JBS R,b CALL k JMP k MOV A,k OR A,k AND A,k XOR A,k RETL k SUB A,k INT PAGE k ADD A,k
OPERATION R-AA R-AR R-1A R-1R AvVRA AvVRR A & RA A & RR A RA A RR A + RA A + RR RA RR /RA /RR R+1A R+1R R-1A, skip if zero R-1R, skip if zero R(n)A(n-1) R(0)C, CA(7) R(n)R(n-1) R(0)C, CR(7) R(n)A(n+1) R(7)C, CA(0) R(n)R(n+1) R(7)C, CR(0) R(0-3)A(4-7) R(4-7)A(0-3) R(0-3)R(4-7) R+1A, skip if zero R+1R, skip if zero 0R(b) 1R(b) if R(b)=0, skip if R(b)=1, skip PC+1[SP] (Page, k) PC (Page, k)PC k A Av kA A & kA A kA kA, [Top of Stack]PC k-AA Z,C,DC PC+1[SP], 001HPC KR5 k+AA
0 0110 01rr rrrr 0 0110 10rr rrrr 0 0110 11rr rrrr 0 0111 00rr rrrr 0 0 0 0 0111 0111 0111 100b 01rr 10rr 11rr bbrr rrrr rrrr rrrr rrrr
0 101b bbrr rrrr 0 0 1 1 1 1 1 1 1 1 1 1 110b 111b 00kk 01kk 1000 1001 1010 1011 1100 1101 1110 1110 bbrr bbrr kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk 0000 1000 rrrr rrrr kkkk kkkk kkkk kkkk kkkk kkkk kkkk kkkk 0001 kkkk
1 1111 kkkk kkkk
* This specification is subject to be changed without notice.
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EM78P860 8 -BIT MICRO-CONTROLLER
VII.8 CODE Option Register The chip has one CODE option register which is not part of the normal program memory. The option bits cannot be accessed during normal program execution. 7 6 5 4 3 2 1 /POVD 0 -
* Bit 0 : unsed * Bit 1 ( /POVD ) : Power on voltage detector. 0 : enable 1 : disable /POVD 1 0 1.8V reset no yes power on reset yes yes 3.6V detect no reset yes yes 3.6V detect control by RA(5) yes yes sleep mode current 1A 15A
* Bit 2~7 : unused, must be "0"s. VII.9 LCD Driver The chip can drive LCD directly and has 60 segments and 16 commons that can drive 60*16 dots totally. LCD block is made up of LCD driver , display RAM, segment output pins , common output pins and LCD operating power supply pins. Duty , bias , the number of segment , the number of common and frame frequency are determined by LCD mode register . LCD control register. The basic structure contains a timing control which uses the basic frequency 32.768KHz to generate the proper timing for different duty and display access. RE register is a command register for LCD driver, the LCD display ( disable, enable, blanking) is controlled by LCD_C and the driving duty and bias is decided by LCD_M and the display data is stored in data RAM which address and data access controlled by registers IOCB and IOCC.
32.768KHz IOCB LCD timing control IOCC RAM
RE(LCD_C,LCD_M)
LCD duty control Display data control
Bias control
LCD commom control
LCD SEGMENT control
Vdd-Vlcd
COM
SEG
Fig. 13 LCD DRIVER CONTROL
* This specification is subject to be changed without notice.
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EM78P860 8 -BIT MICRO-CONTROLLER
1. LCD Driver Control RE(LCD Driver Control)(initial state "00000000") 7 6 5 4 3 2 LCD_C2 1 LCD_C1 0 LCD_M
* Bit0 (LCD_M):LCD_M decides the methods, including duty, bias, and frame frequency. * Bit1~Bit2 (LCD_C#):LCD_C# decides the LCD display enable or blanking. change the display duty must set the LCD_C to "00". LCD_C2,LCD_C1 00 01 11 2. LCD display area The LCD display data is stored in the data RAM . The relation of data area and COM/SEG pin is as below: COM15 ~ COM8 40H (Bit15 ~ Bit8) 41H : : 7BH 7CH 7DH 7EH 7FH * IOCB(LCD Display RAM address) 7 6 LCDA6 5 LCDA5 4 LCDA4 3 LCDA3 2 LCDA2 1 LCDA1 0 LCDA0 COM7 ~ COM0 00H (Bit7 ~ Bit0) 01H : : 3BH 3CH 3DH 3EH 3FH LCD Display Control change duty Disable(turn off LCD) Blanking LCD display enable LCD_M 0 1 : : duty 1/16 1/8 : : bias 1/4 1/4
SEG0 SEG1 : : SEG59 empty empty empty empty
Bit 0 ~ Bit 6 select LCD Display RAM address up to 120. LCD RAM can be write whether in enable or disable mode and read only in disable mode. * IOCC(LCD Display data) : Bit 0 ~ Bit 8 are LCD data. 3. LCD COM and SEG signal * COM signal : The number of COM pins varies according to the duty cycle used, as following: in 1/8 duty mode COM8 ~ COM15 must be open. in 1/16 duty mode COM0 ~ COM15 pins must be used.
* This specification is subject to be changed without notice.
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EM78P860 8 -BIT MICRO-CONTROLLER
1/8 1/16
COM0 o o
COM1 o o
COM2 o o
COM3 o o
COM4 COM5 o o o o
COM6 o o
COM7 COM8 o x o o
.. .. ..
COM15 x o
x:open,o:select * SEG signal: The 60 segment signal pins are connected to the corresponding display RAM address 00h to 3Bh. The high byte and the low byte bit7 down to bit0 are correlated to COM15 to COM0 respectively. When a bit of display RAM is 1, a select signal is sent to the corresponding segment pin, and when the bit is 0 , a non-select signal is sent to the corresponding segment pin. * COM, SEG and Select/Non-select signal is shown as following:
frame
com0 ... com7 VDD V1 V2 V3 VLCD VDD V1 V2 V3 VLCD VDD V1 V2 V3 VLCD VDD V1 V2 V3 VLCD dark VDD V1 V2 V3 VLCD
com0
com1
com2
seg
seg
light
Fig. 14 Lcd wave 1/4 bias, 1/8 duty
* This specification is subject to be changed without notice.
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EM78P860 8 -BIT MICRO-CONTROLLER
Fig. 15 Lcd wave 1/4 bias, 1/16 duty
* This specification is subject to be changed without notice.
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EM78P860 8 -BIT MICRO-CONTROLLER
4.
LCD Bias control IOCE (Bias Control Register) 7 6 5 4 Bias3 3 Bias2 2 Bias1 1 0
Bit 2~4 (Bias1~Bias3) Control bits used to choose LCD operation voltage . LCD operate voltage 000 001 010 011 100 101 110 111 * Bit 5~7 unused Vop (VDD 5V) 0.60 VDD 0.66 VDD 0.74 VDD 0.82 VDD 0.87 VDD 0.93 VDD 0.96 VDD 1.00 VDD VDD=5V 3.0 V 3.3 V 3.7 V 4.0 V 4.4 V 4.7 V 4.8 V 5.0 V
Fig. 16 LCD bias circuit
* This specification is subject to be changed without notice.
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EM78P860 8 -BIT MICRO-CONTROLLER
VIII. ABSOLUTE MAXIMUM RATINGS
Rating DC supply voltage Input voltage Operating temperature range Sym. VDD VIN TA Value -0.3 to 6 -0.5 to VDD+0.5 0 to 70 Unit V V C
IX. DC ELECTRICAL CHARACTERISTICS
(TA= 0C~70C, VDD = 5V5%; VSS = 0V)
Parameter Input Leakage Current for input pins Input Leakage Current for bi-directional pins Input High Voltage Input Low voltage Input High Threshold Voltage Input Low Threshold Voltage Clock Input High Voltage Clock Input Low Voltage Key scan Input High Voltage Key scan Input Low Voltage Output High Voltage (port5,6,7,8) (port9) Output Low Voltage (port5,6,7,8) (port9) Com Voltage drop Segment Voltage drop LCD Drive Reference Voltage Pull-high Current Power Down Current IDLE mode current Low Clock Current Sym. IIL1 IIL2 VIH VIL VIHT VILT VIHX VILX VHscan VLscan VOH1 Condition VIN = VDD, VSS VIN = VDD, VSS 2.5 0.8 /RESET, TCC, RDET1 /RESET, TCC, RDET1 OSCI OSCI Port6 for key scan Port6 for key scan IOH = 1.6 mA IOH = 6 mA IOL = 1.6 mA IOL = 6 mA I O = 50 A I O = 50 A Contrast adjustment Pull-high active input pin at VSS All input and I/O pin at VDD, output pin floating, WDT disabled All input and I/O pin at VDD, output pin floating, WDT disabled,LCD enable CLK=32.768 KHz, All input and I/O pin at VDD, output pin floating, WDT disabled, LCD enable /RESET=HIGH, CLK=3.679MHz, output pin floating 3.5 1.5 3.5 1.5 2.4 2.4 0.4 0.4 2.9 3.8 2.0 0.8 Min. Typ. Max. Unit 1 A 1 A V V V V V V V V V V V V V V
VOL1
VCOM VSEG VLCD IPH ISB1 ISB-1 ISB2
-
-
-50
-100 1 15 50
-240
A A A A
Operating Supply Current
ICC
1.2
mA
* This specification is subject to be changed without notice.
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EM78P860 8 -BIT MICRO-CONTROLLER
X.
AC ELECTRICAL CHARACTERISTIC ( TA = 0 ~ 70C, VDD = 5V,VSS = 0V )
Parameter Input CLK duty cycle Instruction cycle time Device delay hold time TCC input period Watchdog timer period Sym. Dclk Tins Tdrh Ttcc Twdt Condition 45 32.768K 3.679M Note 1 TA = 25C Min. 50 Typ. 55 60 550 Max. % Unit s s ns ms
18 (Tin+20)/N 18
ms
Note 1: N = selected prescaler ratio.
* This specification is subject to be changed without notice.
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EM78P860 8 -BIT MICRO-CONTROLLER
XI. TIMING DIAGRAMS
AC Test Input/Output Waveform
2.4 2.0 0.8 0.45 2.0 TEST PONITS 0.8
AC Testing : Input is driven at 2.4V for logic "1", and 0.45V for logic "0". Timing measurements are made at 2.0V for logic "1", and 0.8V for logic "0". RESET Timing (CLK="0")
NOP Instruction 1 Executed
CLK
/RESET
Tdrh
TCC Input Timing (CLK="0")
Tins
CLK
TCC
Ttcc
Fig. 17 AC timing
* This specification is subject to be changed without notice.
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EM78P860 8 -BIT MICRO-CONTROLLER
XII. APPLICATION CIRCUIT
kEYPAD VDD I/O LOBAT /RESET BATTERY DETECTOR POWER ON RESET CD POWER SUPPLY
EM78P860
EMC78860 LCD COMMON
TEST GND XIN 32768 XOUT PLLC 0.01 30p 30p
SEGMENT
Fig. 18 Application circuit for data bank
* This specification is subject to be changed without notice.
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